Recently, electrostatically defined quantum dots have become of increasing interest because of their applications in quantum information processing,^[1–3] single-electron logic circuits,^[4] high-sensitivity detection,^[5,6] quantum dot cellular automata,^[7,8] etc. These devices have great advantages, such as stable characteristics, simple device structure, high operating temperature, and high compatibility of their fabrication process with integrated circuits.^[9,10] For the operation of these devices, it is important to control the coupling capacitances between the quantum dots and the effective device structures, which are determined by charge configurations in the quantum dots. In the most popular quantum dot structures comprised of nanowire or two-dimensional electron gas, the coupling capacitances can be controlled by gate biases, which can modulate the tunnel barriers around the quantum dots. Thus, extracting capacitances around the quantum dots is a vital aspect for guiding the design of device structure and the analysis of its characteristics.^[11–14]

Since the device size becomes so small that it is difficult to directly measure ultra-small capacitances, it is necessary to explore a simple and efficient method of measuring capacitances. By measuring the transfer currents with the gate pulses, Inokawa et al. have presented a simple test structure for extracting capacitances at room temperature.^[15] According to their test results of a silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistor (MOSFET) structure, they pointed out that the transfer current was not only proportional to the gate pulse frequency, but also linearly dependent on the drain voltage. However, we find experimentally that the transfer current does not linearly depend on the drain voltage for the bulk silicon device. Then, an improved method is presented to extract the capacitances of the test structure, which can be used not only for SOI devices but also for the bulk silicon ones.

The rest of this paper is organized in four sections. In Section 2, the test device structure and the capacitance network are presented. In Section 3, the capacitance extraction method is proposed by analyzing the relation between the transfer current and the voltage of each electrode. In Section 4, the measured results and the extracted capacitance values are provided. Finally, in Section 5 some conclusions are drawn from this work.

Figure 1(a) shows the cross-sectional view of the fabricated silicon nanowire MOSFET by a 65-nm bulk CMOS process. The two lower polysilicon gates (denoted as LG1 and LG2) cross a narrow silicon nanowire to create potential profiles that act as tunneling barriers for the electron transfer process. The region in the nanowire between the two lower gates forms a charge island (that is, a quantum dot). The two lower MOSFETs and the entire nanowire are covered with an upper polysilicon gate (UG), which serves as an input gate for controlling the potential of the dot and a field plate for inducing an inversion layer extending from the source to the drain. This structure is efficient for shielding electromagnetic disturbance in a single electron transfer or a quantum logic operation due to the screening effect of the UG. The lower gate length L, the channel width W, the gate spacing S, the thickness of UG oxide, and the oxide thickness beneath the LGs are 70, 110, 170, 640, and 5 nm respectively.

Fig. 1.

	Figure Option ViewDownloadNew Window
	Fig. 1. (color online) (a) Cross-sectional view of the measured device structure, (b)diagram of the capacitance network around the dot, and (c) top-view scanning electron microscope image before UG formation.

An equivalent circuit with six mutual capacitances is depicted in Fig. 1(b), where , , , , , and are the capacitances between the island and the UG, LG1, LG2, source, drain, and substrate, respectively. The six capacitances can be divided into two groups. One is called ‘operable capacitances’, including , , and . With the operation of these operable capacitances, the electron number and the potential profile on the dot can be changed conveniently. The other is called ‘non-operable capacitances’, including , , and . They are usually biased at the fixed voltages in the charge transfer process. Figure 1(c) shows the top-view scanning electron microscope image before the UG formation.

The measured drain currents of the charge transfer device with high-frequency clock pulses are obtained by using the Agilent 81110A and 4156C. The pulse sequences for UG, LG1, and LG2 are shown in Fig. 2(a). The high and low bias levels of UG are denoted as and respectively. The threshold voltage for UG MOSFET is extracted as from the measured – curve at the biasing voltages of other terminals for LG1, for LG2, for the source, for the drain and for the substrate, respectively.^[16] Thus, in all the subsequent measurements, the inequality must hold in order to keep the nanowire channel in an inversion state. The two quarter period pulses with a half period shift are applied to the lower gates to turn the channel on and off alternatively, and the threshold voltages of the two lower MOSFETs should be between their high and low bias levels ( , . The pulse frequency varies from 0.1 MHz to 5 MHz while their rise and fall times are kept at 18 ns, and such pulses can be treated approximately as square waves. All the measurements are performed at room temperature.

Fig. 2.

	Figure Option ViewDownloadNew Window
	Fig. 2. (color online) (a) Pulse sequence for electron transfer operation and (b) corresponding potential diagrams between source and drain.

The charge transfer mode is shown in Fig. 2(b). In step (i), LG1 MOSFET is in an on state while LG2 MOSFET is in an off state, electrons enter into the silicon wire from the source; then the two channels beneath the LG1 and LG2 MOSFETs are closed (see step (ii) in Fig. 2(b)), some of those electrons are confined on the quantum dot (the charge quantity on the dot is denoted as Q ₁ in this case); next, LG1 is turned off while LG2 is turned on in step (iii), the electrons can be transferred into the drain from the dot; in step (iv), the channel between the LG1 and LG2 is closed again, and some electrons are confined on the quantum dot (the charge quantity on the dot is denoted asQ ₂ in this case). The difference between Q ₁ and Q ₂, i.e., , indicates the number of electrons transferred from the source into the drain in one period of the clock pulses.

In the charge transfer mode, there are charges Q ₁ (or confined on the dot when the voltage of LG1 (or LG2) changes from the high level to the low level (see Fig. 2).

In step (ii) of Fig. 2(b), when the source is grounded, the charge quantity Q ₁ is expressed as^[15] 1 where is replaced by as LG1 MOSFET is at the above threshold. The equals the original threshold voltage ( in the DC measurement, i.e., , for the potential of the dot is zero since the dot is connected to the source at the previous moment in step (i) of Fig. 2(b).

Similarly, in step (iv) of Fig. 2(b), the charge quantity Q ₂ is expressed as^[15] 2 where is replaced by when LG2 MOSFET is on the above threshold. However, is raised from the original threshold voltage ( in the DC measurement roughly by , i.e. , for the potential of the dot is since the dot is connected to the drain at the previous moment in step (iii) of Fig. 2(b).

The transferred charge is the difference between Q ₁ and Q ₂, 3 where , , and is the total capacitance of the dot and defined as 4

The transfer current can be defined as the net charge quantity transferred per second from the source to the drain. Thus, the differential charge is expressed as 5 where f is the frequency of the clock pulse.

By combining Eqs. (3) and (5), we may derive the transfer current as follows: 6

Firstly, the two fringing capacitances and C are extracted. The transfer current versus is measured when or is changed but , , and f are kept constant. From Eq. (6), the two fringing capacitances and at a fixed drain bias are expressed by 7 where or is the slope of curve or at a given drain voltage, respectively.

Similarly, the transfer current versus is measured when is changed but / , , , and f are kept constant. From Eq. (6), the capacitance at a fixed drain bias is expressed by 8 where is the slope of the curve at a given drain voltage.

Next, the total capacitance is extracted. The transfer current versus is measured when f is changed while , , , and are kept constant. It is worth pointing out that the threshold voltages and change with the drain voltage , especially for the bulk MOS devices, thus the drain current does not linearly depend on the drain voltage (see Eq. (6)). For varying , we will obtain different . Here, we extract at a fixed drain voltage. According to Eq. (6), we can develop the following equation: 9 where is the slope of the curve at a fixed drain bias. We can extract from Eq. (9).

If the drain voltage is restricted in a very small range ( , , the threshold voltages and can be assumed to be the constants approximately. On this condition, equation (6) can be rewritten as follows: 10 when and are varying while , , , and f are kept constant. Thus, is extracted from the contour of between and and expressed as 11

Finally, and are extracted. On the basis of Eq. (4) and assuming that , the equation is obtained as follows: 12

Figure 3(a) shows the plot of threshold voltage versus drain voltage of LG1 MOSFET when , , , and . It is obvious that the threshold voltage is a function of drain voltage . From Fig. 3(a), the threshold voltage has a maximal value at about , and decreases rapidly as changes to more negative values from the maximal point while decreases slowly as has more positive values. Similarly, the threshold voltage of LG2 MOSFET is a function of the drain voltage as shown in Fig. 3(b) when , , , and , and its maximal value point also appears at about . The dependence of and on may be mainly caused by the change of substrate surface state as the drain voltage changes. Thus, the transfer current does not linearly depend on the drain voltage , as discussed in the previous section. We further infer that these capacitances abound the dot must be dependent on the drain bias. Therefore, the capacitances must be extracted only at a fixed drain bias, which is called the work-point-bias (WPB). In the following extraction processes, all the WPB is set to be , which is the common drain bias in the DC measurement.

Fig. 3.

	Figure Option ViewDownloadNew Window
	Fig. 3. (color online) (a)Threshold voltage vs. drain voltage for LG1 MOSFET and (b) LG2 MOSFET at direct current measurement. These relations can be fitted as quadratic curves.

Figure 4(a) shows the curves at different low bias levels of LG1 from −2 to −1.6 V in steps of 0.1 V when , , , , , and f = 2 MHz. We obtain the transfer currents , −0.094, −0.325, −0.554, −0.778 pA for , −1.9, −1.8, −1.7, −1.6 V respectively, where the slope scatter points are shown in the inset of Fig. 4(a). The fringing capacitance between the LG1 and the dot is extracted as by the linear fitting method. Figure 4(b) shows the curves at different low bias levels of LG2 from −2 V to −1.6 V in steps of 0.1 V when , , , , , and f = 2 MHz. The transfer currents are , −0.528, −0.333, −0.083, 0.203 pA for , −1.9, −1.8, −1.7, −1.6 V respectively. The fringing capacitance between the LG2 and the dot is from the linear fitting of these transfer current data shown in the inset of Fig. 4(b). Figure 4(c) shows the curves when the difference between and changes from 5.0 V to −5.0 V in steps of −2.5 V at , , , , and f = 2 MHz. From the transfer currents , −0.259, −0.325, −0.415, −0.569 pA for , 2.5, 0, −2.5, −5 V respectively, is obtained by the linear fitting method as shown in the inset of Fig. 4(c).

Fig. 4.

	Figure Option ViewDownloadNew Window
	Fig. 4. (color online) Transfer currents versus drain voltages for changing (a) , (b) (b), and (c) , in which the inset figures show the corresponding slope of versus (a) , (b) and (c) at the WPB respectively.

Figure 5 shows the electron transfer characteristics of the device for gate pulse frequencies from 0.1 MHz to 5 MHz when , , , , and . All the six curves are partially bent, which means that the transfer current is not proportional to the drain bias in the whole range, mainly resulting from the threshold voltages and dependent on the drain voltage . However, the device conductance is approximately proportional to the pulse frequency f as shown in the inset of Fig. 55, indicating that an approximate fixed quantity of charges is transferred in one period of the gate pulses.^[15] The inset of Fig. 5 shows the transfer current , −0.769, −0.665, −0.469, −0.274, −0.052 pA for f = 5, 4, 3, 2, 1, 0.1 MHz respectively and the corresponding linear fitting curve. Based on the slope of the fitting curve and Eq. (9), the total capacitance is obtained to be .

Fig. 5.

	Figure Option ViewDownloadNew Window
	Fig. 5. (color online) Transfer currents vs. drain voltages for changing gate pulse frequencies from 0.1 MHz to 5 MHz, in which the inset (in color) shows the corresponding slope of versus f at the WPB .

Figure 6 shows the – curves at different substrate bias voltages from −1 V to −0.6 V in steps of 0.1 V when , , , , and f = 2 MHz. The current value is selected as a reference current, at which the corresponding drain voltages are obtained to be , −0.0346, −0.0327, −0.00769, 0.01 V when , −0.9, −0.8, −0.7, −0.6 V by the linear interpolation method, which is shown in the inset of Fig. 6. From the slope of the fitting curve in the inset of Fig. 6 and Eq. (10), is obtained. Finally, the two capacitances and are calculated to be .

Fig. 6.

	Figure Option ViewDownloadNew Window
	Fig. 6. (color online) Transfer currents vs. drain voltages for changing substrate bias from −1 V to −0.6 V, in which the inset shows the current contour between the drain voltage and the substrate voltage at the reference current .

It is worth noting that the capacitance or , which could be called ‘barrier capacitance’ from the source/drain to the dot,^[17] is more than three times the fringing capacitance or . It means that the barrier capacitance dominates the total capacitance of the dot. In the test device structure, the silicon dioxide layer thickness beneath the lower gate is 5 nm. If the oxide layer decreases, the fringing capacitances may increase. In general transfer operation, the barrier capacitances would be kept constant, but at the same time the clock pulses are biased on the lower gates to push the charges into (out of) the dot. Thus, the fringing capacitances and , together with , are called the operable capacitances in the previous section, for the electron number on the dot and the potential of the dot could be modulated by the effects of these capacitances.

According to the quantum dot structure in the silicon nanowire MOSFET, we present an improved method to extract the coupling capacitances around the dot. Simple formulas to describe the transfer current and the electrode biases are obtained to calculate the total capacitance and the coupling capacitances. By modulating the two barrier potentials beneath the lower gates with phase-shifted pulse voltages, the transfer current is measured and analyzed. The transfer current is proportional to the pulse frequency, but it does not linearly depend on the drain voltage. The barrier capacitances dominate the total capacitance around the dot, but the fringing capacitances are very important for manipulating the charge transfer from the source to the drain. This capacitance extraction technique could be used to determine the capacitance parameters not only in the bulk silicon devices, but also in the SOI MOSFETs.

The authors would like to thank Prof. Hiroshi Inokawa from the Electronics Research Institute of Shizuoka University for his helpful experiments and discussions. We also wish to thank Guoli Li from Hunan University for the revision of the manuscript.